Motorola 68000 Instruction Set

Mnemonic	Description	Operands	Data Size			Condition Codes
Mnemonic	Description	Operands	Data Size			X	N	Z	V	C
ABCD	add BCD with extend	Dx, Dy -(Ax), -(Ay)	B			*	U	*	U	*
ADD	add binary	Dn,<ea> <ea>,Dn	B	W	L	*	*	*	*	*
ADDA	add binary to An	<ea>, An		W	L
ADDI	add immediate	#x, An	B	W	L	*	*	*	*	*
ADDQ	add 3-byte immediate	#<1-8>,<ea>	B	W	L	*	*	*	*	*
ADDX	add extended	Dy, Dx -(Ay), -(Ax)	B	W	L	*	*	*	*	*
AND	bit-wise and	<ea>, Dn Dn, <ea>	B	W	L		*	*	0	0
ANDI	bit wise and with immediate	#<data>, <ea>	B	W	L		*	*	0	0
ASL	arithmetic shift left	#<1-8>, Dy Dx, Dy <ea>	B	W	L	*	*	*	*	*
ASR	arithmetic shift right	#<1-8>, Dy Dx, Dy <ea>	B	W	L	*	*	*	*	*
Bcc	conditional branch	Bcc.S <label> Bcc.W <label>	B	W
BCHG	test a bit and change	Dn, <ea> #<data>, <ea>	B		L			*
BCLR	test a bit and clear	Dn, <ea> #<data>, <ea>	B		L			*
BSET	test a bit and set	Dn, <ea> #<data>, <ea>	B		L			*
BSR	branch to subroutine	BSR.S <label> BSR.W <label>	B	W
BTST	bit test	Dn, <ea> #<data>, <ea>	B		L			*
CHK	check Dn against bounds	<ea>, Dn		W			*	U	U	U
CLR	clear	<ea>	B	W	L		0	1	0	0
CMP	compare	<ea>, Dn	B	W	L		*	*	*	*
CMPA	compare address	<ea>, An		W	L		*	*	*	*
CMPI	compare immediate	#<data>, <ea>	B	W	L		*	*	*	*
CMPM	compare memory	(Ax)+, (Ay)+	B	W	L		*	*	*	*
DBcc	looping instruction	DBcc Dn, <label>		W
DIVS	divide signed	<ea>, Dn		W			*	*	*	0
DIVU	divide unsigned	<ea>, Dn		W			*	*	*	0
EOR	exclusive OR	Dn, <ea>	B	W	L		*	*	0	0
EORI	exclusive OR immediate	#<data>, <ea>	B	W	L		*	*	0	0
EXG	exchange any two registers	Rx, Ry			L
EXT	sign extended	Dn		W	L		*	*	0	0
ILLEGAL	raise illegal instruction exception
JMP	jump to effective address	<ea>
JSR	jump to subroutine	<ea>
LEA	load effective address	<ea>, An			L
LINK	allocate stack frame	An, #<displacement>
LSL	logical shift left	Dx, Dy #<1-8>, Dy <ea>	B	W	L	*	*	*	0	*
LSR	logical shift right	Dx, Dy #<1-8>, Dy <ea>	B	W	L	*	*	*	0	*
MOVE	between effective address	<ea>, <ea>	B	W	L		*	*	0	0
MOVE	to CCR	<ea>, CCR		W		I	I	I	I	I
MOVE	to CCR	SR, <ea>		W		I	I	I	I	I
MOVE	from SR	<ea>, SR		W
MOVE	USP to/from address register	USP, An An, USP			L
MOVEA	move address	<ea>, An		W	L
MOVEM	move multiple	<reg list>, <ea> <ea>, <reg list>		W	L
MOVEP	move peripheral	Dn, x(An) x(An), Dn		W	L
MOVEQ	move 8-bit immediate	#<-128,+127>, Dn			L		*	*	0	0
MULS	multiply signed	<ea>, Dn		W			*	*	0	0
MULU	multiply unsigned	<ea>, Dn		W			*	*	0	0
NBCD	negate BCD	<ea>	B			*	U	*	U	*
NEG	negate	<ea>	B	W	L	*	*	*	*	*
NEGX	negate with extend	<ea>	B	W	L	*	*	*	*	*
NOP	no operation
NOT	form one's complement	<ea>	B	W	L		*	*	0	0
OR	bit-wise or	<ea>, Dn Dn, <ea>	B	W	L		*	*	0	0
ORI	bit-wiese or with immediate	#<data>, <ea>	B	W	L		*	*	0	0
PEA	push effective address	<ea>			L
RESET	reset all external devices
ROL	rotate left	#<1-8>, Dy Dx, Dy <ea>	B	W	L		*	*	0	*
ROR	rotate right	#<1-8>, Dy Dx, Dy <ea>	B	W	L		*	*	0	*
ROXL	rotate left with extend	#<1-8>, Dy Dx, Dy <ea>	B	W	L	*	*	*	0	*
ROXR	rotate right with extend	#<1-8>, Dy Dx, Dy <ea>	B	W	L	*	*	*	0	*
RTE	return from exception					I	I	I	I	I
RTR	return and restore					I	I	I	I	I
RTS	return from subroutine
SBCD	subtract BCD with extend	Dx, Dy -(Ax), -(Ay)	B			*	U	*	U	*
Scc	set to -1 if true, else 0	<ea>	B
STOP	enable and wait for interrupts	#<data>				I	I	I	I	I
SUB	subtract binary	Dn, <ea> <ea>, Dn	B	W	L	*	*	*	*	*
SUBA	subtract binary from address	<ea>, An		W	L
SUBI	subtract immediate	#x, <ea>	B	W	L	*	*	*	*	*
SUBQ	subtract 3-bit immediate	#<1-8>, <ea>	B	W	L	*	*	*	*	*
SUBX	subtract extended	Dy, Dx -(Ay), -(Ax)	B	W	L	*	*	*	*	*
SWAP	swap words of Dn	Dn		W			*	*	0	0
TAS	test and set MSB & set N/Z bits	<ea>	B				*	*	0	0
TRAP	execute trap exception	#<vector>
TRAPV	trapv exception with V bit set
TST	test for negative or zero	<ea>	B	W	L		*	*	0	0
UNLK	deallocate stack frame	An

Symbol	Meaning
<blank>	set accordingly to result of operation
*	not affected
0	cleared
1	set
U	outcome (state after operation) undefined
I	set by immediate data
<ea>	effective address operand
<data>	immediate data
<label>	assember label
<vector>	TRAP instruction exception vector (0-15)
<reg lst>	MOVEM instruction register specification list
<displacement>	LINK instruction negative displacement

Addressing Modes	Syntax
data register direct	Dn
address register direct	An
address register indirect	(An)
address register indirect with post-increment	(An)+
address register indirect with pre-decrement	-(An)
address register indirect with displacement	w(An)
address register indirect with index	b(An, Rx)
absolute short	w
absolute long	l
program counter with displacement	w(PC)
program counter with index	b(PC, Rx)
immediate	#x
status register	SR

Legend
Dn	data register 0-7
An	address register 0-7
b	8-bit constant
w	16-bit constant
l	32-bit constant
x	8-, 16- or 32-bit constant
Rx	index register specification
		Dn.W	low 16 bits of data register
		Dn.L	all 32 bits of data register
		An.W	low 16 bits of address register
		An.L	all 32 bits of address register

Condition Codes for Bcc, DBcc and Scc Instructions.
Condition Codes set after CMP D0, D1 Instruction.

Realationship	Unsigned	Signed
D1 < D0	CS carry bit set	LT les than
D1 <= D0	LS lower or same	LE less or equal
D1 == D0	EQ equal (Z-bit set)	EQ equal (Z-bit set)
D1 != D0	NE not equal (Z-bit cleared)	NE not equal (Z-bit cleared)
D1 > D0	HI higher than	GT greater than
D1 >= D0	CC carry bit clear	GE greater than or equal
	PL plus (N-bit cleared)	MI minus (N-bit set)
	VC V-bit cleared (no overflow)	VS V-bit set (overflow)
	RA branch always
DBcc only	F never terminate (DBRA is an alternate to DBF)
	T always terminate
	ST always set
	SF never set

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